FIG. 23 illustrates a part of a read-only semiconductor memory device 110, which includes a memory cell array 111, a column switch 112, a reference level generation circuit 113 and a sense amplifier 114.
The memory cell array 111 includes a plurality (only one is illustrated in FIG. 23) word lines WL, a plurality of bit lines BL and a plurality of memory cells MC provided at intersections of the word lines WL and the bit lines BL. Each memory cell MC is a cell transistor T1 including a drain coupled to the corresponding bit line BL and a gate coupled to the corresponding word line WL.
The column switch 112 includes a plurality of switch circuits CS including first terminals coupled to the bit lines BL, respectively. A column selection signal COL is supplied to a gate of each switch circuit CS. A second terminal of each switch circuit CS is coupled to the sense amplifier 114 via a data bit line DB.
The reference level generation circuit 113 includes a dummy word line DWL, dummy bit lines DBL0, DBL1, one dummy cell DMCa provided in correspondence with the two dummy bit lines DBL0, DBL1 and N-channel MOS transistors TN. First terminals of the N-channel MOS transistors TN are respectively coupled to the dummy bit lines DBL0, DBL1. The dummy cell DMCa is a dummy transistor DTa including a drain coupled to the dummy bit lines DBL0 DBL1, a source coupled to a low-voltage power supply and a gate coupled to the dummy word line DWL. The transistor TN includes a gate coupled to a high-voltage power supply VDD and a second terminal coupled to a dummy common line DC.
In the case of reading data from an arbitrary memory cell MC of the semiconductor memory device 110, one word line WL and one bit line BL are activated. Data written in the memory cell MC coupled to the activated word line WL and bit line BL is read to the bit line BL. That is, the voltage of the bit line BL changes in accordance with the data written in the memory cell MC. The charge of the bit line BL is transmitted to the sense amplifier 114 through the data bit line DB in accordance with a column selection signal COL. At this time, in the reference level generation circuit 113, the dummy word line DWL and the dummy bit lines DBL0, DBL1 are activated and the dummy transistor DTa is turned on. The voltage of the dummy common line DC is changed by the turned-on dummy transistor DTa. The voltage of the dummy common line DC is supplied as a reference level to the sense amplifier 114. The sense amplifier 114 amplifies a voltage difference between the data bit line DB and the dummy common line DC and outputs an amplified signal as read data AX.
Since the reference level generation circuit 113 generates the reference level of the sense amplifier 114 in this way, the semiconductor memory device 110 may read data utilizing the sense amplifier 114 of a differential amplification type even in the case of reading the data of the memory cell MC by a single-phase bit line.
A technology relating to the above conventional technology is disclosed in Japanese Laid-Open Utility Model Publication No. 55-036479.
However, for the reference level generation circuit 113 to generate a desired reference level, the dummy bit lines DBL0, DBL1 need to be respectively formed to reproduce a load (parasitic capacity) of the bit line BL coupled to the memory cell MC. Thus, there is a problem of increasing a layout area by as much as the dummy bit lines DBL0, DBL1 are formed.